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lt3758/lt3758a 1 3758afd applications n automotive n telecom n industrial n wide input voltage range: 5.5v to 100v n positive or negative output voltage programming with a single feedback pin n current mode control provides excellent transient response n programmable operating frequency (100khz to 1mhz) with one external resistor n synchronizable to an external clock n low shutdown current < 1a n internal 7.2v low dropout voltage regulator n programmable input undervoltage lockout with hysteresis n programmable soft-start n small 10-lead dfn (3mm 3mm) and msope packages typical application description high input voltage, boost, flyback, sepic and inverting controller the lt ? 3758/lt3758 a are wide input range, current mode, dc/dc controllers which are capable of generating either positive or negative output voltages. they can be configured as either a boost, flyback, sepic or inverting converter. the lt3758/lt3758a drive a low side external n-channel power mosfet from an internal regulated 7.2 v supply. the fixed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. the operating frequency of lt3758/lt3758a can be set with an external resistor over a 100 khz to 1 mhz range, and can be synchronized to an external clock using the sync pin. a minimum operating supply voltage of 5.5 v, and a low shutdown quiescent current of less than 1 a, make the lt3758/lt3758a ideally suited for battery- powered systems. the lt3758/lt3758a feature soft-start and frequency foldback functions to limit inductor current during start - up and output short-circuit. the lt3758a has improved load transient performance compared to the lt3758. 12v output nonisolated flyback power supply features sense lt3758 v in d sn v in 36v to 72v c in 2.2f100v x7r 63.4k200khz gate fbx gnd intv cc shdn /uvlo sync rtss 0.022f100v t1 1,2,3 (series) 4,5,6(parallel) 1m44.2k 0.47f 100pf 10k 10nf 0.030 15.8k1% 105k1% c vcc 4.7f10v x5r v out 12v1.2a 3758 ta01 c out 47fx5r 6.2k d1 sw m1 5.1 1n4148 v c l , lt , lt c , lt m , linear technology, the linear logo and burst mode are registered trademarks and no r sense and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. patents pending. downloaded from: http:///
lt3758/lt3758a 2 3758afd pin configuration absolute maximum ratings v in , shdn / uvlo ( note 7) ...................................... 100 v intv cc .................................................... v in + 0.3 v, 20v gate ........................................................ intv cc + 0.3 v sync .......................................................................... 8v v c , ss ......................................................................... 3v rt ............................................................................................... 1.5 v sense .................................................................... 0.3 v fbx ................................................................. C6 v to 6v (note 1) top view dd package 10-lead (3mm 3mm) plastic dfn 10 96 7 8 45 11 3 2 1 v in shdn /uvlo intv cc gate sense v c fbx ss rt sync t jmax = 125c, ja = 43c/w exposed pad (pin 11) is gnd, must be soldered to pcb 12 3 4 5 v c fbx ss rt sync 109 8 7 6 v in shdn /uvlo intv cc gate sense top view mse package 10-lead plastic msop 11 t jmax = 150c, ja = 40c/w exposed pad (pin 11) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt3758edd#pbf lt3758edd#trpbf ldnk 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3758idd#pbf lt3758idd#trpbf ldnk 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3758emse#pbf lt3758emse#trpbf ltdnm 10-lead (3mm 3mm) plastic msop C40c to 125c lt3758imse #pbf lt3758imse#trpbf ltdnm 10-lead (3mm 3mm) plastic msop C40c to 125c LT3758HMSE#pbf LT3758HMSE#trpbf ltdnm 10-lead (3mm 3mm) plastic msop C40c to 150c lt3758mpmse #pbf lt3758mpmse#trpbf ltdnm 10-lead (3mm 3mm) plastic msop C55c to 150c lt3758aedd#pbf lt3758aedd#trpbf lggs 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3758aidd#pbf lt3758aidd#trpbf lggs 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3758aemse#pbf lt3758aemse#trpbf ltggk 10-lead (3mm 3mm) plastic msop C40c to 125c lt3758aimse#pbf lt3758aimse#trpbf ltggk 10-lead (3mm 3mm) plastic msop C40c to 125c lt3758ahmse#pbf lt3758ahmse#trpbf ltggk 10-lead (3mm 3mm) plastic msop C40c to 150c lt3758ampmse#pbf lt3758ampmse#trpbf ltggk 10-lead (3mm 3mm) plastic msop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating junction temperature range ( notes 2, 8) lt 3758 e/ lt 3758 ae ........................... C40 c to 125 c lt 3758 i/ lt 3758 ai ............................. C40 c to 125 c lt 3758 h/ lt 3758 ah .......................... C40 c to 150 c lt 3758 mp / lt 3758 amp ..................... C55 c to 150 c storage temperature range dfn .................................................... C65 c to 125 c msop ................................................ C65 c to 150 c lead temperature ( soldering , 10 sec ) msop ............................................................... 300 c downloaded from: http:///
lt3758/lt3758a 3 3758afd electrical characteristics the l denotes the specifications which apply over the full operating temp- erature range, otherwise specifications are at t a = 25c. v in = 24v, shdn /uvlo = 24v, sense = 0v, unless otherwise noted. parameter conditions min typ max units v in operating range 5.5 100 v v in shutdown i q shdn /uvlo = 0v shdn /uvlo = 1.15v 0.1 1 6 a a v in operating i q v c = 0.3v, r t = 41.2k 1.75 2.2 ma v in operating i q with internal ldo disabled v c = 0.3v, r t = 41.2k, intv cc = 7.5v 350 400 a sense current limit threshold l 100 110 120 mv sense input bias current current out of pin C65 a error amplifier fbx regulation voltage (v fbx(reg) ) fbx > 0v (note 3) fbx < 0v (note 3) l l 1.569 C0.816 1.6 C0.800 1.631 C0.784 v v fbx overvoltage lockout fbx > 0v (note 4) fbx < 0v (note 4) 6 7 8 11 10 14 % % fbx pin input current fbx = 1.6v (note 3) fbx = C0.8v (note 3) C10 70 100 10 na na transconductance g m (?i vc /?fbx) (note 3) 230 s v c output impedance (note 3) 5 m v fbx line regulation (?v fbx /[?v in ? v fbx(reg) ]) fbx > 0v, 5.5v < v in < 100v (notes 3, 6) fbx < 0v, 5.5v < v in < 100v (notes 3, 6) 0.006 0.005 0.025 0.03 %/v %/v v c current mode gain (?v vc /?v sense ) 5.5 v/v v c source current v c = 1.5v C15 a v c sink current fbx = 1.7v fbx = C0.85v 12 11 a a oscillator switching frequency r t = 41.2k to gnd, fbx = 1.6v r t = 140k to gnd, fbx = 1.6v r t = 10.5k to gnd, fbx = 1.6v 270 300 100 1000 330 khz khz khz rt voltage fbx = 1.6v 1.2 v minimum off-time 220 ns minimum on-time 220 ns sync input low 0.4 sync input high 1.5 ss pull-up current ss = 0v, current out of pin C10 a low dropout regulator intv cc regulation voltage l 7 7.2 7.4 v intv cc undervoltage lockout threshold falling intv cc uvlo hysteresis 4.3 4.5 0.5 4.7 v v intv cc overvoltage lockout threshold 17.5 v intv cc current limit v in = 100v v in = 20v 11 16 50 22 ma ma intv cc load regulation (?v intvcc / v intvcc ) 0 < i intvcc < 10ma, v in = 8v C1 C0.4 % intv cc line regulation (?v intvcc / [?v in ? v intvcc ]) 8v < v in < 100v 0.005 0.02 %/v dropout voltage (v in C v intvcc ) v in = 6v, i intvcc = 10ma 500 mv downloaded from: http:///
lt3758/lt3758a 4 3758afd electrical characteristics the l denotes the specifications which apply over the full operating temp- erature range, otherwise specifications are at t a = 25c. v in = 24v, shdn /uvlo = 24v, sense = 0v, unless otherwise noted. parameter conditions min typ max units intv cc current in shutdown shdn /uvlo = 0v, intv cc = 8v 16 a intv cc voltage to bypass internal ldo 7.5 v logic inputsshdn /uvlo threshold voltage falling v in = intv cc = 8v l 1.17 1.22 1.27 v shdn /uvlo input low voltage i vin drops below 1a 0.4 v shdn /uvlo pin bias current low shdn /uvlo = 1.15v 1.7 2 2.5 a shdn /uvlo pin bias current high shdn /uvlo = 1.33v 10 100 na gate drivert r gate driver output rise time c l = 3300pf (note 5), intv cc = 7.5v 22 ns t f gate driver output fall time c l = 3300pf (note 5), intv cc = 7.5v 20 ns gate output low (v ol ) 0.05 v gate output high (v oh ) intv cc C0.05 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3758e/lt3758ae are guaranteed to meet performance specifications from the 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3758i/lt3758ai are guaranteed over the full C40c to 125c operating junction temperature range. the lt3758h/lt3758ah are guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. the lt3758mp/lt3758amp are 100% tested and guaranteed over the full C55c to 150c operating junction temperature range. note 3: the lt3758/lt3758a are tested in a feedback loop which servos v fbx to the reference voltages (1.6v and C0.8v) with the v c pin forced to 1.3v. note 4: fbx overvoltage lockout is measured at v fbx(overvoltage) relative to regulated v fbx(reg) . note 5: rise and fall times are measured at 10% and 90% levels. note 6: shdn /uvlo = 1.33v when v in = 5.5v. note 7: for v in below 6v, the shdn /uvlo pin must not exceed v in . note 8: the lt3758/lt3758a include overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. downloaded from: http:///
lt3758/lt3758a 5 3758afd temperature (c) C75 C50 1580 1585 regulated feedback voltage (v) 1590 1605 1600 0 50 75 1595 C25 25 100 150 125 3758 g01 v in = 100v v in = 24v v in = 8v v in = intv cc = 5.5v shdn /uvlo = 1.33v temperature (c) regulated feedback voltage (mv) C802 C800 C798 C790 C792C794 C804 C796 3758 g02 C75 C50 0 50 75 C25 25 100 150 125 v in = 100v v in = 24v v in = 8v v in = intv cc = 5.5v shdn /uvlo = 1.33v typical performance characteristics positive feedback voltage vs temperature, v in negative feedback voltage vs temperature, v in quiescent current vs temperature, v in t a = 25c, unless otherwise noted. C75 C50 0 50 75 C25 25 100 150 125 temperature (c) 1.5 quiescent current (ma) 1.6 1.91.8 1.7 3758 g03 v in = 100v v in = 24v v in = intv cc = 5.5v dynamic quiescent current vs switching frequency r t vs switching frequency normalized switching frequency vs fbx fbx voltage (v) C0.8 0 normalized frequency (%) 20 40 60 80 120 C0.4 0 0.4 0.8 3758 g06 1.2 1.6 100 switching frequency (khz) 0 0 i q (ma) 15 20 35 300 500 600 700 10 5 25 30 100 200 400 900 800 1000 3758 g04 c gate = 3300pf switching frequency (khz) 0 10 r t (k) 100 1000 300 500 600 700 100 200 400 900 800 1000 3758 g05 downloaded from: http:///
lt3758/lt3758a 6 3758afd switching frequency vs temperature sense current limit threshold vs temperature sense current limit threshold vs duty cycle shdn /uvlo threshold vs temperature shdn /uvlo current vs voltage shdn /uvlo hysteresis current vs temperature C75 C50 0 50 75 C25 25 100 150 125 temperature (c) 100 sense threshold (mv) 105 110 115 120 3758 g08 duty cycle (%) 0 95 sense threshold (mv) 105 20 40 80 60 115 100 110 100 3758 g09 shdn /uvlo voltage (v) 0 0 shdn /uvlo current (a) 20 20 60 40 80 40 50 10 30 100 3758 g11 C75 C50 0 50 75 C25 25 100 150 125 temperature (c) 1.6 i shdn /uvlo (a) 1.8 2.0 2.2 2.4 3758 g12 C75 C50 0 50 75 C25 25 100 150 125 temperature (c) 270 switching frequency (khz) 280 290 300 310 330 3758 g07 320 r t = 41.2k C75 C50 0 50 75 C25 25 100 150 125 temperature (c) 1.18 shdn /uvlo voltage (v) 1.22 1.24 1.26 1.28 1.20 3758 g10 shdn /uvlo falling shdn /uvlo rising typical performance characteristics t a = 25c, unless otherwise noted. downloaded from: http:///
lt3758/lt3758a 7 3758afd typical performance characteristics t a = 25c, unless otherwise noted. intv cc line regulation intv cc dropout voltage vs current, temperature intv cc vs temperature intv cc minimum output current vs v in intv cc load regulation C75 C50 0 50 75 C25 25 100 150 125 temperature (c) 7.0 intv cc (v) 7.1 7.2 7.3 7.4 3758 g13 v in (v) 0 intv cc voltage (v) 90 7.257.20 20 30 50 10 40 60 70 80 100 7.15 7.10 7.30 3758 g16 1 0 5 10 20 30 10 100 45 40 15 25 35 t j = 150c v in (v) 3758 g14 intv cc current (ma) intv cc = 6v intv cc = 4.7v intv cc load (ma) 0 6.8 7 7.1 7.2 7.3 10 20 25 6.9 5 15 3758 g15 intv cc voltage (v) v in = 8v 0 4 2 6 8 10 intv cc load (ma) dropout voltage (mv) 500 600 300 400 200 100 0 1000 900800 700 3758 g17 150c 25c 0c C55c 75c v in = 6v 125c gate drive rise and fall time vs intv cc typical start-up waveforms fbx frequency foldback waveforms during overcurrent intv cc (v) 3 time (ns) 20 25 15 10 9 6 12 15 5 0 30 3758 g19 c l = 3300pf rise time fall time 2ms/div see typical application: 18v to 72v input, 24v output sepic converter v out 10v/div i l1a + i l1b 1a/div 3758 g20 v in = 48v 50s/div v out 20v/div v sw 50v/div i l1a + i l1b 2a/div 3758 g21 v in = 48v see typical application: 18v to 72v input, 24v output sepic converter gate drive rise and fall time vs c l c l (nf) 0 time (ns) 60 70 8050 40 5 15 10 20 25 30 10 0 30 9020 3758 g18 rise time intv cc = 7.2v fall time downloaded from: http:///
lt3758/lt3758a 8 3758afd pin functions v c ( pin 1): error amplifier compensation pin. used to stabilize the voltage loop with an external rc network.fbx ( pin 2): positive and negative feedback pin. re- ceives the feedback voltage from the external resistor divider across the output. also modulates the switching frequency during start-up and fault conditions when fbx is close to gnd. ss ( pin 3): soft - start pin. this pin modulates compensation pin voltage ( v c ) clamp . the soft-start interval is set with an external capacitor. the pin has a 10 a ( typical) pull-up current source to an internal 2.5 v rail. the soft-start pin is reset to gnd by an undervoltage condition at shdn / uvlo, an intv cc undervoltage or overvoltage condition or an internal thermal lockout.rt ( pin 4): switching frequency adjustment pin. set the frequency using a resistor to gnd. do not leave this pin open.sync ( pin 5): frequency synchronization pin. used to synchronize the switching frequency to an outside clock. if this feature is used, an r t resistor should be chosen to program a switching frequency 20% slower than the sync pulse frequency. tie the sync pin to gnd if this feature is not used. sync is bypassed when fbx is close to gnd. sense ( pin 6): the current sense input for the control loop. kelvin connect this pin to the positive terminal of the switch current sense resistor in the source of the nfet . the negative terminal of the current sense resistor should be connected to gnd plane close to the ic. gate ( pin 7): n-channel mosfet gate driver output. switches between intv cc and gnd. driven to gnd when ic is shut down, during thermal lockout or when intv cc is above or below the overvoltage or uv thresholds, respectively. intv cc ( pin 8): regulated supply for internal loads and gate driver. supplied from v in and regulated to 7.2 v ( typi- cal). intv cc must be bypassed with a minimum of 4.7 f capacitor placed close to pin. intv cc can be connected directly to v in , if v in is less than 17. 5v. intv cc can also be connected to a power supply whose voltage is higher than 7.5 v, and lower than v in , provided that supply does not exceed 17.5v. shdn /uvlo ( pin 9): shutdown and undervoltage detect pin. an accurate 1.22 v ( nominal) falling threshold with externally programmable hysteresis detects when power is okay to enable switching. rising hysteresis is generated by the external resistor divider and an accurate internal 2a pull-down current. an undervoltage condition resets sort-start. tie to 0.4 v, or less, to disable the device and reduce v in quiescent current below 1a. v in ( pin 10): input supply pin. must be locally bypassed with a 0.22 f, or larger, capacitor placed close to the pin. exposed pad ( pin 11): ground. this pin also serves as the negative terminal of the current sense resistor. the exposed pad must be soldered directly to the local ground plane. downloaded from: http:///
lt3758/lt3758a 9 3758afd block diagram figure 1. lt3758 block diagram working as a sepic converter l1 r1 r3 r4 m1 r2 l2 fbx 1.22v 2.5v d1 c dc c in v out c out2 c out1 c vcc intv cc v in r sense v isense ? + + v in i s1 2a 10 8 7 1 9 shdn /uvlo internal regulator and uvlo tsd 165?c a10 q3 v c 17.5v 5v up4.5v down a8 uvlo i s2 10a i s3 c c1 c c2 r c driver slope sense gnd gate 110mv sr1 +? +? current limit ramp generator 7.2v ldo ? + ? +? r o s 2.5v rt r t ss c ss sync 1.28v 1.2v fbx fbx 1.6v ?0.8v +? +? 2 3 5 4 + ? +? 6 11 ramp pwmcomparator frequency foldback 100khz-1mhz oscillator freqprog 3758 f01 ? ++ q1 a1a2 1.72v ?0.88v + ? + ? a11a12 +? a3 a4 a5 a6 g2 g5 g6 a7 a9 q2 g4 g3 g1 v c d2 r5 8k d3 downloaded from: http:///
lt3758/lt3758a 10 3758afd applications information main control loop the lt3758 uses a fixed frequency, current mode control scheme to provide excellent line and load regulation. op- eration can be best understood by referring to the block diagram in figure 1. the start of each oscillator cycle sets the sr latch ( sr1) and turns on the external power mosfet switch m1 through driver g2. the switch current flows through the external current sensing resistor r sense and generates a voltage proportional to the switch current. this current sense voltage v isense ( amplified by a5) is added to a stabilizing slope compensation ramp and the resulting sum ( slope) is fed into the positive terminal of the pwm comparator a7. when slope exceeds the level at the negative input of a7 (v c pin), sr1 is reset, turning off the power switch. the level at the negative input of a7 is set by the error amplifier a 1 ( or a2) and is an amplified version of the difference between the feedback voltage ( fbx pin) and the reference voltage (1.6 v or ?0.8 v, depending on the configuration). in this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. the lt3758 has a switch current limit function. the current sense voltage is input to the current limit comparator a6. if the sense pin voltage is higher than the sense current limit threshold v sense(max) (110 mv, typical), a6 will reset sr1 and turn off m1 immediately. the lt3758 is capable of generating either positive or negative output voltage with a single fbx pin. it can be configured as a boost, flyback or sepic converter to gen- erate positive output voltage, or as an inverting converter to generate negative output voltage. when configured as a sepic converter, as shown in figure 1, the fbx pin is pulled up to the internal bias voltage of 1.6 v by a volt- age divider ( r1 and r2) connected from v out to gnd. comparator a2 becomes inactive and comparator a1 performs the inverting amplification from fbx to v c . when the lt3758 is in an inverting configuration, the fbx pin is pulled down to ?0.8 v by a voltage divider connected from v out to gnd. comparator a1 becomes inactive and comparator a2 performs the noninverting amplification from fbx to v c . the lt3758 has overvoltage protection functions to protect the converter from excessive output voltage overshoot during start-up or recovery from a short-circuit condition. an overvoltage comparator a 11 ( with 20 mv hysteresis) senses when the fbx pin voltage exceeds the positive regulated voltage (1.6 v) by 8% and provides a reset pulse. similarly, an overvoltage comparator a12 (with 10 mv hysteresis) senses when the fbx pin voltage exceeds the negative regulated voltage (?0.8 v) by 11% and provides a reset pulse. both reset pulses are sent to the main rs latch ( sr1) through g6 and g5. the power mosfet switch m1 is actively held off for the duration of an output overvoltage condition. programming turn-on and turn-off thresholds with the shdn /uvlo pin the shdn /uvlo pin controls whether the lt3758 is enabled or is in shutdown state. a micropower 1.22 v reference, a comparator a10 and a controllable current source i s1 allow the user to accurately program the supply voltage at which the ic turns on and off. the falling value can be accurately set by the resistor dividers r3 and r4. when shdn /uvlo is above 0.4 v, and below the 1.22 v threshold, the small pull-down current source i s1 ( typical 2a) is active. the purpose of this current is to allow the user to program the rising hysteresis. the block diagram of the comparator and the external resistors is shown in figure 1. the typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: v v i n , f a lli n g = 1. 22 ? ( r 3 + r 4) r 4 v v i n , r i s i n g = 2a ? r 3 + v i n , f a lli n g for applications where the shdn /uvlo pin is only used as a logic input, the shdn /uvlo pin can be connected directly to the input voltage v in through a 1 k resistor for always-on operation. downloaded from: http:///
lt3758/lt3758a 11 3758afd applications information intv cc regulator bypassing and operation an internal, low dropout ( ldo) voltage regulator produces the 7.2 v intv cc supply which powers the gate driver, as shown in figure 1. the lt3758 contains an undervoltage lockout comparator a 8 and an overvoltage lockout com - parator a 9 for the intv cc supply. the intv cc undervoltage ( uv) threshold is 4.5 v ( typical), with 0.5 v hysteresis, to ensure that the mosfets have sufficient gate drive voltage before turning on. the logic circuitry within the lt3758 is also powered from the internal intv cc supply . the intv cc overvoltage threshold is set to be 17.5 v (typical) to protect the gate of the power mosfet. when intv cc is below the uv threshold, or above the overvolt- age threshold, the gate pin will be forced to gnd and the soft-start operation will be triggered. the intv cc regulator must be bypassed to ground im- mediately adjacent to the ic pins with a minimum of 4.7 f ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate driver. in an actual application, most of the ic supply current is used to drive the gate capacitance of the power mosfet. the on - chip power dissipation can be a significant concern when a large power mosfet is being driven at a high fre- quency and the v in voltage is high. it is important to limit the power dissipation through selection of mosfet and/ or operating frequency so the lt3758 does not exceed its maximum junction temperature rating. the junction tem- perature t j can be estimated using the following equations : t j = t a + p ic ? ja t a = ambient temperature ja = junction-to-ambient thermal resistance p ic = ic power consumption = v in ? ( i q + i drive ) i q = v in operation i q = 1.6ma i drive = average gate drive current = f ? q g f = switching frequencyq g = power mosfet total gate charge the lt3758 uses packages with an exposed pad for en- hanced thermal conduction. with proper soldering to the exposed pad on the underside of the package and a full copper plane underneath the device, thermal resistance ( ja ) will be about 43 c/w for the dd package and 40 c/w for the mse package. for an ambient board temperature of t a = 70 c and maximum junction temperature of 125 c, the maximum i drive ( i drive(max) ) of the dd package can be calculated as: i drive(max) = (t j ? t a ) ( ja ? v in ) ? i q = 1.28w v in ? 1.6ma the lt3758 has an internal intv cc i drive current limit function to protect the ic from excessive on-chip power dissipation. the i drive current limit decreases as the v in increases ( see the intv cc minimum output current vs v in graph in the typical performance characteristics section). if i drive reaches the current limit, intv cc voltage will fall and may trigger the soft-start. based on the preceding equation and the intv cc minimum output current vs v in graph, the user can calculate the maximum mosfet gate charge the lt3758 can drive at a given v in and switch frequency. a plot of the maximum q g vs v in at different frequencies to guarantee a minimum 4.7v intv cc is shown in figure 2. figure 2. recommended maximum q g vs v in at different frequencies to ensure intv cc higher than 4.7v v in (v) 1 q g (nc) 10 100 3758 f02 0 20 40 80 120 140 60 100 300khz 1mhz downloaded from: http:///
lt3758/lt3758a 12 3758afd applications information as illustrated in figure 2, a trade-off between the operating frequency and the size of the power mosfet may be needed in order to maintain a reliable ic junction temperature. prior to lowering the operating frequency, however, be sure to check with power mosfet manufacturers for their most recent low q g , low r ds(on) devices. power mosfet manufacturing technologies are continually improving, with newer and better performance devices being introduced almost yearly. an effective approach to reduce the power consumption of the internal ldo for gate drive is to tie the intv cc pin to an external voltage source high enough to turn off the internal ldo regulator. if the input voltage v in does not exceed the absolute maximum rating of both the power mosfet gate-source voltage ( v gs ) and the intv cc overvoltage lockout threshold voltage (17.5 v), the intv cc pin can be shorted directly to the v in pin. in this condition, the internal ldo will be turned off and the gate driver will be powered directly from the input voltage v in . with the intv cc pin shorted to v in , however, a small current ( around 16 a) will load the intv cc in shutdown mode. for applications that require the lowest shutdown mode input supply current, do not connect the intv cc pin to v in . in sepic or flyback applications, the intv cc pin can be connected to the output voltage v out through a blocking diode, as shown in figure 3, if v out meets the following conditions: 1. v out < v in (pin voltage) 2. v out < 17.5v 3. v out < maximum v gs rating of power mosfet a resistor r vcc can be connected, as shown in figure 3, to limit the inrush current from v out . regardless of whether or not the intv cc pin is connected to an external voltage source, it is always necessary to have the driver circuitry bypassed with a 4.7 f low esr ceramic capacitor to ground immediately adjacent to the intv cc and gnd pins. operating frequency and synchronization the choice of operating frequency may be determined by on-chip power dissipation, otherwise it is a trade-off between efficiency and component size. low frequency operation improves efficiency by reducing gate drive cur- rent and mosfet and diode switching losses. however, lower frequency operation requires a physically larger inductor. switching frequency also has implications for loop compensation. the lt3758 uses a constant - frequency architecture that can be programmed over a 100 khz to 1000khz range with a single external resistor from the rt pin to ground, as shown in figure 1. the rt pin must have an external resistor to gnd for proper operation of the lt3758. a table for selecting the value of r t for a given operating frequency is shown in table 1. table 1. timing resistor (r t ) value switching frequency (khz) r t (k) 100 140 200 63.4 300 41.2 400 30.9 500 24.3 600 19.6 700 16.5 800 14 900 12.1 1000 10.5 the operating frequency of the lt3758 can be synchronized to an external clock source. by providing a digital clock signal into the sync pin, the lt3758 will operate at the sync clock frequency. if this feature is used, an r t resistor should be chosen to program a switching frequency 20% slower than sync pulse frequency. it is recommended the sync pulse have a minimum pulse width of 200 ns. tie the sync pin to gnd if this feature is not used. figure 3. connecting intv cc to v out c vcc 4.7f v out 3758 f03 intv cc gnd lt3758 r vcc d vcc downloaded from: http:///
lt3758/lt3758a 13 3758afd applications information duty cycle consideration switching duty cycle is a key variable defining converter operation. as such, its limits must be considered. minimum on-time is the smallest time duration that the lt3758 is capable of turning on the power mosfet. this time is generally about 220 ns ( typical ) ( see minimum on-time in the electrical characteristics table). in each switching cycle, the lt3758 keeps the power switch off for at least 220ns ( typical ) ( see minimum off-time in the electrical characteristics table). the minimum on-time and minimum off-time and the switching frequency define the minimum and maximum switching duty cycles a converter is able to generate:minimum duty cycle = minimum on-time ? frequency maximum duty cycle = 1 ? ( minimum off - time ? frequency ) programming the output voltage the output voltage v out is set by a resistor divider, as shown in figure 1. the positive and negative v out are set by the following equations: v out,positive = 1.6v ? 1 + r2 r1 ?? ? ?? ? v out,negative = ?0.8v ? 1 + r2 r1 ?? ? ?? ? the resistors r1 and r2 are typically chosen so that the error caused by the current flowing into the fbx pin during normal operation is less than 1% ( this translates to a maximum value of r1 at about 158k). in the applications where v out is pulled up by an external positive power supply, the fbx pin is also pulled up through the r 2 and r 1 network. make sure the fbx does not exceed its absolute maximum rating (6 v). the r5, d2, and d3 in figure 1 provide a resistive clamp in the positive direction . to ensure fbx is lower than 6 v, choose sufficiently large r1 and r2 to meet the following condition: 6v ? 1 + r2 r1 ?? ? ?? ? + 3.5v ? r2 8k ? > v out(max) where v out(max) is the maximum v out that is pulled up by an external power supply. soft-start the lt3758 contains several features to limit peak switch currents and output voltage ( v out ) overshoot during start-up or recovery from a fault condition. the primary purpose of these features is to prevent damage to external components or the load. high peak switch currents during start-up may occur in switching regulators. since v out is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. a large surge current may cause inductor saturation or power switch failure. the lt3758 addresses this mechanism with the ss pin. as shown in figure 1, the ss pin reduces the power mosfet current by pulling down the v c pin through q2. in this way the ss allows the output capacitor to charge gradually toward its final value while limiting the start-up peak currents. the typical start-up waveforms are shown in the typical performance characteristics section. the inductor current i l slewing rate is limited by the soft-start function. besides start-up ( with shdn /uvlo), soft-start can also be triggered by the following faults: 1. intv cc > 17.5v 2. intv cc < 4.5v 3. thermal lockout any of these three faults will cause the lt3758 to stop switching immediately. the ss pin will be discharged by q3. when all faults are cleared and the ss pin has been discharged below 0.2 v, a 10 a current source i s2 starts charging the ss pin, initiating a soft-start operation. the soft-start interval is set by the soft-start capacitor selection according to the equation: t ss = c ss ? 1.25v 10a downloaded from: http:///
lt3758/lt3758a 14 3758afd applications information fbx frequency foldback when v out is very low during start-up or a gnd fault on the output, the switching regulator must operate at low duty cycles to maintain the power switch current within the current limit range, since the inductor current decay rate is very low during switch off time. the minimum on- time limitation may prevent the switcher from attaining a sufficiently low duty cycle at the programmed switching frequency. so, the switch current will keep increasing through each switch cycle, exceeding the programmed current limit. to prevent the switch peak currents from exceeding the programmed value, the lt3758 contains a frequency foldback function to reduce the switching frequency when the fbx voltage is low ( see the normal- ized switching frequency vs fbx graph in the typical performance characteristics section). during frequency foldback, external clock synchroniza- tion is disabled to prevent interference with frequency reducing operation.thermal lockout if lt3758 die temperature reaches 165 c ( typical), the part will go into thermal lockout. the power switch will be turned off. a soft-start operation will be triggered. the part will be enabled again when the die temperature has dropped by 5c (nominal).loop compensation loop compensation determines the stability and transient per formance. the lt3758/lt3758a use current mode control to regulate the output which simplifies loop com- pensation. the lt3758a improves the no-load to heavy load transient response, when compared to the lt3758. new internal circuits ensure that the transient from not switching to switching at high current can be made in a few cycles. the optimum values depend on the converter topology, the component values and the operating condi- tions ( including the input voltage, load current, etc.). to compensate the feedback loop of the lt3758/lt3758a, a series resistor-capacitor network is usually connected from the v c pin to gnd. figure 1 shows the typical v c compensation network. for most applications, the capacitor should be in the range of 470 pf to 22 nf, and the resistor should be in the range of 5 k to 50 k. a small capacitor is often connected in parallel with the rc compensation network to attenuate the v c voltage ripple induced from the output voltage ripple through the internal error amplifier. the parallel capacitor usually ranges in value from 10 pf to 100pf. a practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensa- tion network to optimize the performance. stability should then be checked across all operating conditions, including load current, input voltage and temperature. sense pin programming for control and protection, the lt3758 measures the power mosfet current by using a sense resistor ( r sense ) between gnd and the mosfet source. figure 4 shows a typical waveform of the sense voltage ( v sense ) across the sense resistor. it is important to use kelvin traces between the sense pin and r sense , and to place the ic gnd as close as possible to the gnd terminal of the r sense for proper operation. figure 4. the sense voltage during a switching cycle 3758 f04 v sense(peak) ? v sense = ??? v sense(max) v sense t dt s v sense(max) t s downloaded from: http:///
lt3758/lt3758a 15 3758afd applications information due to the current limit function of the sense pin, r sense should be selected to guarantee that the peak current sense voltage v sense(peak) during steady state normal operation is lower than the sense current limit threshold ( see the electrical characteristics table). given a 20% margin, v sense(peak) is set to be 80 mv. then, the maximum switch ripple current percentage can be calculated using the following equation: c = ? v sense 80mv ? 0.5 ? ? v sense c is used in subsequent design examples to calculate in- ductor value . ? v sense is the ripple voltage across r sense . the lt3758 switching controller incorporates 100 ns timing interval to blank the ringing on the current sense signal immediately after m1 is turned on. this ringing is caused by the parasitic inductance and capacitance of the pcb trace, the sense resistor, the diode, and the mosfet. the 100ns timing interval is adequate for most of the lt3758 applications. in the applications that have very large and long ringing on the current sense signal, a small rc filter can be added to filter out the excess ringing. figure 5 shows the rc filter on the sense pin. it is usually suf- ficient to choose 22 for r f lt and 2.2 nf to 10 nf for c flt . keep r f lt s resistance low. remember that there is 65 a (typical) flowing out of the sense pin. adding r f lt will affect the sense current limit threshold: v sense_ilim = 110mv C 65a ? r f lt application circuits the lt3758 can be configured as different topologies. the first topology to be analyzed will be the boost converter, followed by the flyback, sepic and inverting converters.boost converter: switch duty cycle and frequency the lt3758 can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. remember that boost con- verters are not short-circuit protected. under a shorted output condition, the inductor current is limited only by the input supply capability. for applications requiring a step-up converter that is short-circuit protected, please refer to the applications information section covering sepic converters.the conversion ratio as a function of duty cycle is: v out v in = 1 1 ? d in continuous conduction mode (ccm). for a boost converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage ( v out ) and the input voltage ( v in ). the maximum duty cycle ( d max ) occurs when the converter has the minimum input voltage: d max = v out ? v in(min) v out discontinuous conduction mode ( dcm) provides higher conversion ratios at a given frequency at the cost of reduced efficiencies and higher switching currents.boost converter: inductor and sense resistor selection for the boost topology, the maximum average inductor current is: i l(max) = i o(max) ? 1 1 ? d max then, the ripple current can be calculated by: ? i l = c ? i l(max) = c ? i o(max) ? 1 1 ? d max figure 5. the rc filter on the sense pin c flt 3758 f05 lt3758 r flt r sense m 1 sense gate gnd downloaded from: http:///
lt3758/lt3758a 16 3758afd applications information the constant c in the preceding equation represents the percentage peak-to-peak ripple current in the inductor, relative to i l(max) . the inductor ripple current has a direct effect on the choice of the inductor value. choosing smaller values of ? i l requires large inductances and reduces the current loop gain ( the converter will approach voltage mode). accepting larger values of ? i l provides fast transient response and allows the use of low inductances, but results in higher input current ripple and greater core losses. it is recommended that c fall within the range of 0.2 to 0.6. given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value of the boost converter can be determined using the following equation: l = v in(min) ? i l ? f ? d max the peak and rms inductor current are: i l(peak) = i l(max) ? 1 + c 2 ?? ? ?? ? i l(rms) = i l(max) ? 1 + c 2 12 based on these equations, the user should choose the inductors having sufficient saturation and rms current ratings. set the sense voltage at i l(peak) to be the minimum of the sense current limit threshold with a 20% margin. the sense resistor value can then be calculated to be: r sense = 80mv i l(peak) boost converter: power mosfet selection important parameters for the power mosfet include the drain-source voltage rating ( v ds ), the threshold voltage (v gs(th) ), the on-resistance ( r ds(on) ), the gate to source and gate to drain charges ( q gs and q gd ), the maximum drain current ( i d( max ) ) and the mosfet s thermal resistances (r jc and r ja ). the power mosfet will see full output voltage, plus a diode forward voltage, and any additional ringing across its drain-to-source during its off-time. it is recommended to choose a mosfet whose b vdss is higher than v out by a safety margin ( a 10 v safety margin is usually sufficient). the power dissipated by the mosfet in a boost converter is : p fet = i 2 l( max ) ? r ds ( on ) ? d max + 2 ? v 2 out ? i l( max ) ? c rss ? f/1a the first term in the preceding equation represents the conduction losses in the device, and the second term, the switching loss. c rss is the reverse transfer capacitance, which is usually specified in the mosfet characteristics . for maximum efficiency, r ds(on) and c rss should be minimized. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following equation: t j = t a + p fet ? ja = t a + p fet ? ( jc + ca ) t j must not exceed the mosfet maximum junction temperature rating. it is recommended to measure the mosfet temperature in steady state to ensure that absolute maximum ratings are not exceeded.boost converter: output diode selection to maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desirable. the peak reverse voltage that the diode must withstand is equal to the regulator output voltage plus any additional ringing across its anode-to-cathode during the on-time. the average forward current in normal operation is equal to the output current, and the peak current is equal to: i d(peak) = i l(peak) = 1 + c 2 ?? ? ?? ? ? i l(max) it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out by a safety margin ( a 10 v safety margin is usually sufficient).the power dissipated by the diode is: p d = i o(max) ? v d and the diode junction temperature is: t j = t a + p d ? r ja downloaded from: http:///
lt3758/lt3758a 17 3758afd applications information figure 6. the output ripple waveform of a boost converter v out (ac) t on ? v esr ringing due tototal inductance (board + cap) ? v cout 3758 f06 t off the output capacitor in a boost regulator experiences high rms ripple currents, as shown in figure 6. the rms ripple current rating of the output capacitor can be determined using the following equation: i rms(cout) i o(max) ? d max 1 ? d max multiple capacitors are often paralleled to meet esr requirements. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the required rms current rating. additional ceramic capaci - tors in parallel are commonly used to reduce the effect of parasitic inductance in the output capacitor, which reduces high frequency switching noise on the converter output.boost converter: input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input, and the input current wave- form is continuous. the input voltage source impedance determines the size of the input capacitor, which is typi- cally in the range of 10 f to 100 f. a low esr capacitor is recommended, although it is not as critical as for the output capacitor. the rms input capacitor ripple current for a boost con- verter is: i rms(cin) = 0.3 ? ? i l flyback converter applications the lt3758 can be configured as a flyback converter for the applications where the converters have multiple outputs, high output voltages or isolated outputs. figure 7 shows a simplified flyback converter. the flyback converter has a very low parts count for mul- tiple outputs, and with prudent selection of turns ratio, can have high output/input voltage conversion ratios with a desirable duty cycle. however, it has low efficiency due to the high peak currents, high peak voltages and consequent power loss. the flyback converter is commonly used for an output power of less than 50w. the r ja to be used in this equation normally includes the r jc for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating . boost converter: output capacitor selection contributions of esr ( equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct output capacitors for a given output ripple voltage. the effect of these three parameters ( esr, esl and bulk c ) on the output voltage ripple waveform for a typical boost converter is illustrated in figure 6. the choice of component(s) begins with the maximum acceptable ripple voltage ( expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step ? v esr and the charging/discharg- ing ? v cout . for the purpose of simplicity, we will choose 2% for the maximum output ripple, to be divided equally between ? v esr and ? v cout . this percentage ripple will change, depending on the requirements of the applica- tion, and the following equations can easily be modified. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the fol- lowing equation: esr cout 0.01 ? v out i d(peak) for the bulk c component, which also contributes 1% to the total ripple: c out i o(max) 0.01 ? v out ? f downloaded from: http:///
lt3758/lt3758a 18 3758afd applications information the flyback converter can be designed to operate either in continuous or discontinuous mode. compared to con- tinuous mode, discontinuous mode has the advantage of smaller transformer inductances and easy loop compen- sation, and the disadvantage of higher peak-to-average current and lower efficiency. to the number of variables involved. the user can choose either a duty cycle or a turns ratio as the start point. the following trade-offs should be considered when select- ing the switch duty cycle or turns ratio, to optimize the converter performance. a higher duty cycle affects the flyback converter in the following aspects:? lower mosfet rms current i sw(rms) , but higher mosfet v ds peak voltage ? lower diode peak reverse voltage, but higher diode rms current i d(rms) ? higher transformer turns ratio (n p /n s ) the choice, d d + d2 = 1 3 (for discontinuous mode operation with a given d3) gives the power mosfet the lowest power stress ( the product of rms current and peak voltage). the choice, d d + d2 = 23 (for discontinuous mode operation with a given d3) gives the diode the lowest power stress ( the product of rms current and peak voltage). an extreme high or low duty cycle results in high power stress on the mosfet or diode, and reduces efficiency. it is recommended to choose a duty cycle between 20% and 80%. figure 7. a simplified flyback converter r sense n p :n s v in c in c sn v sn l p d suggested rcd snubber i d v ds i sw 3758 f07 gate gnd lt3758 sense l s m +? +? r sn d sn + ? + c out + figure 8. waveforms of the flyback converter in discontinuous mode operation 3758 f08 i sw v ds i d t dt s d2t s d3t s i sw(max) i d(max) t s flyback converter: switch duty cycle and turns ratio the flyback converter conversion ratio in the continuous mode operation is: v out v in = n s n p ? d 1 ? d where n s /n p is the second to primary turns ratio. figure 8 shows the waveforms of the flyback converter in discontinuous mode operation. during each switching period t s , three subintervals occur: dt s , d2t s , d3t s . during dt s , m is on, and d is reverse-biased. during d2t s , m is off, and l s is conducting current. both l p and l s currents are zero during d3t s . the flyback converter conversion ratio in the discontinu- ous mode operation is: v out v in = n s n p ? d d2 according to the preceding equations, the user has relative freedom in selecting the switch duty cycle or turns ratio to suit a given application. the selections of the duty cycle and the turns ratio are somewhat iterative processes, due downloaded from: http:///
lt3758/lt3758a 19 3758afd applications information flyback converter: transformer design for discontinuous mode operation the transformer design for discontinuous mode of opera- tion is chosen as presented here. according to figure 8, the minimum d 3 ( d3 min ) occurs when the the converter has the minimum v in and the maximum output power (p out ). choose d3 min to be equal to or higher than 10% to guarantee the converter is always in discontinuous mode operation. choosing higher d3 allows the use of low inductances but results in higher switch peak current. the user can choose a d max as the start point. then, the maximum average primary currents can be calculated by the following equation: i lp(max) = i sw(max) = p out(max) d max ? v in(min) ? h where h is the converter efficiency. if the flyback converter has multiple outputs, p out(max) is the sum of all the output power. the maximum average secondary current is: i ls(max) = i d(max) = i out(max) d2 whered2 = 1 ? d max ? d3 the primary and secondary rms currents are: i lp(rms) = 2 ? i lp(max) ? d max 3 i ls(rms) = 2 ? i ls(max) ? d2 3 according to figure 8, the primary and secondary peak currents are: i lp(peak) = i sw(peak) = 2 ? i lp(max) i ls(peak) = i d(peak) = 2 ? i ls(max) the primary and second inductor values of the flyback converter transformer can be determined using the fol- lowing equations: l p = d 2 max ? v 2 in(min) ? h 2 ? p out(max) ? f l s = d2 2 ? (v out + v d ) 2 ? i out(max) ? f the primary to second turns ratio is: n p n s = l p l s flyback converter: snubber design transformer leakage inductance ( on either the primary or secondary) causes a voltage spike to occur after the mos- fet turn-off. this is increasingly prominent at higher load currents, where more stored energy must be dissipated. in some cases a snubber circuit will be required to avoid overvoltage breakdown at the mosfet ?s drain node. there are different snubber circuits, and application note 19 is a good reference on snubber design. an rcd snubber is shown in figure 7. the snubber resistor value ( r sn ) can be calculated by the following equation: r sn = 2 ? v 2 sn ? v sn ? v out ? n p n s i 2 sw(peak) ? l lk ? f where v sn is the snubber capacitor voltage. a smaller v sn results in a larger snubber loss. a reasonable v sn is 2 to 2.5 times of: v out ? n p n s downloaded from: http:///
lt3758/lt3758a 20 3758afd applications information l lk is the leakage inductance of the primary winding, w hich is usually specified in the transformer characteristics. l lk can be obtained by measuring the primary inductance with the secondary windings shorted. the snubber capacitor value ( c cn ) can be determined using the following equation : c cn = v sn ? v sn ? r cn ? f where ? v sn is the voltage ripple across c cn . a reasonable ?v sn is 5% to 10% of v sn . the reverse voltage rating of d sn should be higher than the sum of v sn and v in(max) . flyback converter: sense resistor selectionin a flyback converter, when the power switch is turned on , the current flowing through the sense resistor ( i sense ) is : i sense = i lp set the sense voltage at i lp(peak) to be the minimum of the sense current limit threshold with a 20% margin. the sense resistor value can then be calculated to be: r sense = 80mv i lp(peak) flyback converter: power mosfet selection for the flyback configuration, the mosfet is selected with a v dc rating high enough to handle the maximum v in , the reflected secondary voltage and the voltage spike due to the leakage inductance. approximate the required mosfet v dc rating using: bv dss > v ds(peak) where v ds(peak) = v in(max) + v sn the power dissipated by the mosfet in a flyback con- verter is: p fet = i 2 m(rms) ? r ds(on) + 2 ? v 2 ds(peak) ? i l(max) ? c rss ? f/1a the first term in this equation represents the conduction losses in the device, and the second term, the switching loss. c rss is the reverse transfer capacitance, which is usually specified in the mosfet characteristics. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following equation: t j = t a + p fet ? ja = t a + p fet ? ( jc + ca ) t j must not exceed the mosfet maximum junction temperature rating. it is recommended to measure the mosfet temperature in steady state to ensure that absolute maximum ratings are not exceeded.flyback converter: output diode selection the output diode in a flyback converter is subject to large rms current and peak reverse voltage stresses. a fast switching diode with a low forward drop and a low reverse leakage is desired. schottky diodes are recommended if the output voltage is below 100v. approximate the required peak repetitive reverse voltage rating v rrm using: v rrm > n s n p ? v in(max) + v out the power dissipated by the diode is: p d = i o(max) ? v d and the diode junction temperature is: t j = t a + p d ? r ja the r ja to be used in this equation normally includes the r jc for the device, plus the thermal resistance from the board to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating . flyback converter: output capacitor selection the output capacitor of the flyback converter has a similar operation condition as that of the boost converter. refer to the boost converter: output capacitor selection section for the calculation of c out and esr cout . the rms ripple current rating of the output capacitors in discontinuous operation can be determined using the following equation: i rms(cout),discontinuous i o(max) ? 4 ? (3 ? d2) 3 ? d2 downloaded from: http:///
lt3758/lt3758a 21 3758afd applications information flyback converter: input capacitor selection the input capacitor in a flyback converter is subject to a large rms current due to the discontinuous primary current. to prevent large voltage transients, use a low esr input capacitor sized for the maximum rms current. the rms ripple current rating of the input capacitors in discontinuous operation can be determined using the following equation: i rms(cin),discontinuous p out(max) v in(min) ? h ? 4 ? (3 ? d max ) 3 ? d max sepic converter applications the lt3758 can be configured as a sepic ( single-ended primary inductance converter), as shown in figure 1. this topology allows for the input to be higher, equal, or lower than the desired output voltage. the conversion ratio as a function of duty cycle is: v out + v d v in = d 1 ? d in continuous conduction mode (ccm). in a sepic converter, no dc path exists between the input and output. this is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. compared to the flyback converter, the sepic converter has the advantage that both the power mosfet and the output diode voltages are clamped by the capacitors ( c in , c dc and c out ), therefore, there is less voltage ringing across the power mosfet and the output diodes. the sepic converter requires much smaller input capacitors than those of the flyback converter. this is due to the fact that, in the sepic converter, the inductor l1 is in series with the input, and the ripple current flowing through the input capacitor is continuous. sepic converter: switch duty cycle and frequency for a sepic converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage ( v out ), the input voltage ( v in ) and the diode forward voltage (v d ). the maximum duty cycle ( d max ) occurs when the converter has the minimum input voltage: d max = v out + v d v in(min) + v out + v d sepic converter: inductor and sense resistor selection as shown in figure 1, the sepic converter contains two inductors: l 1 and l 2. l 1 and l 2 can be independent, but can also be wound on the same core, since identical voltages are applied to l1 and l2 throughout the switching cycle. for the sepic topology, the current through l1 is the converter input current. based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of l1 and l2 are: i l1(max) = i in(max) = i o(max) ? d max 1 ? d max i l2(max) = i o(max) in a sepic converter, the switch current is equal to i l1 + i l2 when the power switch is on, therefore, the maximum average switch current is defined as: i sw(max) = i l1(max) + i l2(max) = i o(max) ? 1 1 ? d max and the peak switch current is: i sw(peak) = 1 + c 2 ?? ? ?? ? ? i o(max) ? 1 1 ? d max the constant c in the preceding equations represents the percentage peak-to-peak ripple current in the switch, rela- tive to i sw(max) , as shown in figure 9. then, the switch ripple current ?i sw can be calculated by: ? i sw = c ? i sw(max) the inductor ripple currents ?i l1 and ?i l2 are identical: ? i l1 = ?i l2 = 0.5 ? ? i sw the inductor ripple current has a direct effect on the choice of the inductor value. choosing smaller values of ?i l requires large inductances and reduces the current loop gain ( the converter will approach voltage mode). downloaded from: http:///
lt3758/lt3758a 22 3758afd applications information accepting larger values of ? i l allows the use of low in- ductances, but results in higher input current ripple and greater core losses. it is recommended that c falls in the range of 0.2 to 0.6. figure 9. the switch current waveform of the sepic converter 3758 f09 ? i sw = ??? i sw(max) i sw t dt s i sw(max) t s where c l1 = ? i l1 i l1(max) i l2(rms) = i l2(max) ? 1 + c 2 l2 12 where c l2 = ? i l2 i l2 (max) based on the preceding equations, the user should choose the inductors having sufficient saturation and rms cur- rent ratings. in a sepic converter, when the power switch is turned on, the current flowing through the sense resistor ( i sense ) is the switch current. set the sense voltage at i sense(peak) to be the minimum of the sense current limit threshold with a 20% margin. the sense resistor value can then be calculated to be: r sense = 80 mv i sw(peak) sepic converter: power mosfet selection for the sepic configuration, choose a mosfet with a v dc rating higher than the sum of the output voltage and input voltage by a safety margin ( a 10 v safety margin is usually sufficient). the power dissipated by the mosfet in a sepic con- verter is: p fet = i 2 sw(max) ? r ds(on) ? d max + 2 ? ( v in(min) + v out ) 2 ? i l(max) ? c rss ? f/1a the first term in this equation represents the conduction losses in the device, and the second term, the switching loss. c rss is the reverse transfer capacitance, which is usually specified in the mosfet characteristics. for maximum efficiency, r ds(on) and c rss should be minimized. from a known power dissipated in the power given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value ( l 1 and l 2 are independent) of the sepic converter can be determined using the following equation: l1 = l2 = v in(min) 0.5 ? ? i sw ? f ? d max for most sepic applications, the equal inductor values will fall in the range of 1h to 100h. by making l 1 = l2, and winding them on the same core, the value of inductance in the preceding equation is re- placed by 2l, due to mutual inductance: l = v in(min) ? i sw ? f ? d max this maintains the same ripple current and energy storage in the inductors. the peak inductor currents are: i l1(peak) = i l1(max) + 0.5 ? ? i l1 i l2(peak) = i l2(max) + 0.5 ? ? i l2 the rms inductor currents are: i l1(rms) = i l1(max) ? 1 + c 2 l1 12 downloaded from: http:///
lt3758/lt3758a 23 3758afd applications information mosfet, its junction temperature can be obtained using the following equation: t j = t a + p fet ? ja = t a + p fet ? ( jc + ca ) t j must not exceed the mosfet maximum junction temperature rating. it is recommended to measure the mosfet temperature in steady state to ensure that absolute maximum ratings are not exceeded.sepic converter: output diode selection to maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable. the average forward current in normal operation is equal to the output current, and the peak current is equal to: i d(peak) = 1 + c 2 ?? ? ?? ? ? i o(max) ? 1 1 ? d max it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out + v in(max) by a safety margin (a 10v safety margin is usually sufficient).the power dissipated by the diode is: p d = i o(max) ? v d and the diode junction temperature is: t j = t a + p d ? r ja the r ja used in this equation normally includes the r jc for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. sepic converter: output and input capacitor selection the selections of the output and input capacitors of the sepic converter are similar to those of the boost converter . please refer to the boost converter: output capacitor selection and boost converter: input capacitor selection sections.sepic converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor ( c dc , as shown in figure 1) should be larger than the maximum input voltage: v cdc > v in(max) c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately ?i o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? v out + v d v in(min) a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . inverting converter applications the lt3758 can be configured as a dual-inductor inverting topology, as shown in figure 10. the v out to v in ratio is: v out ? v d v in = ? d 1 ? d in continuous conduction mode (ccm). figure 10. a simplified inverting converter r sense c dc v in c in l1 d1 c out v out 3758 f10 + gate gnd lt3758 sense l2 m1 + ? + ? + inverting converter: switch duty cycle and frequency for an inverting converter operating in ccm, the duty cycle of the main switch can be calculated based on the negative output voltage ( v out ) and the input voltage ( v in ). the maximum duty cycle ( d max ) occurs when the converter has the minimum input voltage: d max = v out ? v d v out ? v d ? v in(min) downloaded from: http:///
lt3758/lt3758a 24 3758afd inverting converter: inductor, sense resistor, power mosfet, output diode and input capacitor selections the selections of the inductor, sense resistor, power mosfet, output diode and input capacitor of an invert- ing converter are similar to those of the sepic converter. please refer to the corresponding sepic converter sections . inverting converter: output capacitor selection the inverting converter requires much smaller output capacitors than those of the boost, flyback and sepic converters for similar output ripples. this is due to the fact that, in the inverting converter, the inductor l2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. the output ripple voltage is produced by the ripple current of l2 flowing through the esr and bulk capacitance of the output capacitor: ? v out(p ? p) = ? i l2 ? esr cout + 1 8 ? f ? c out ?? ? ?? ? after specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. the esr can be minimized by using high quality x5r or x7r dielectric ceramic capacitors. in many applications, ceramic capacitors are sufficient to limit the output volt- age ripple. the rms ripple current rating of the output capacitor needs to be greater than: i rms(cout) > 0.3 ? ? i l2 inverting converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor ( c dc , as shown in figure 10) should be larger than the maximum input voltage minus the output voltage ( negative voltage): v cdc > v in(max) ? v out c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately ?i o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? d max 1 ? d max a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . board layout the high speed operation of the lt3758 demands careful attention to board layout and component placement. the exposed pad of the package is the only gnd terminal of the ic, and is important for thermal management of the ic. therefore, it is crucial to achieve a good electrical and thermal contact between the exposed pad and the ground plane of the board. for the lt3758 to deliver its full output power, it is imperative that a good thermal path be pro- vided to dissipate the heat generated within the package. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ic and into a copper plane with as much area as possible.to prevent radiation and high frequency resonance prob- lems, proper layout of the components connected to the ic is essential, especially the power paths with higher di/ dt. the following high di/dt loops of different topologies should be kept as tight as possible to reduce inductive ringing: ? in boost configuration, the high di/dt loop contains the output capacitor , the sensing resistor, the power mosfet and the schottky diode. ? in flyback configuration, the high di/dt primary loop contains the input capacitor, the primary winding, the power mosfet and the sensing resistor. the high di/ dt secondary loop contains the output capacitor, the secondary winding and the output diode. ? in sepic configuration, the high di/dt loop contains the power mosfet, sense resistor, output capacitor, schottky diode and the coupling capacitor. ? in inverting configuration, the high di/dt loop contains power mosfet, sense resistor, schottky diode and the coupling capacitor. applications information downloaded from: http:///
lt3758/lt3758a 25 3758afd applications information check the stress on the power mosfet by measuring its drain - to - source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the pc board). beware of inductive ringing, which can exceed the maximum specified voltage rating of the mosfet. if this ringing cannot be avoided, and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche- rated power mosfet. the small-signal components should be placed away from high frequency switching nodes. for optimum load regulation and true remote sensing, the top of the output voltage sensing resistor divider should connect indepen- dently to the top of the output capacitor ( kelvin connec- tion), staying away from any high dv/dt traces. place the divider resistors near the lt3758 in order to keep the high impedance fbx node short. figure 11 shows the suggested layout of the 10 v to 40 v input , 48 v output boost converter in the typical applica- tions section. figure 11. suggested layout of the 10v to 40v input, 48v output boost converter in the typical applications section v in 3758 f11 v out l1 vias to ground plane d1 c out1 c out2 12 87 34 65 m1 c in r c r1 r2 c ss r t r3 r4 c vcc c c1 c c2 lt3758 1 2 3 4 5 9 10 6 7 8 r s downloaded from: http:///
lt3758/lt3758a 26 3758afd applications information table 2. recommended component manufacturers vendor components web address avx capacitors avx.com bh electronics inductors, transformers bhelectronics.com coilcraft inductors coilcraft.com cooper bussmann inductors bussmann.com diodes, inc diodes diodes.com fairchild mosfets fairchildsemi.com general semiconductor diodes generalsemiconductor . com international rectifier mosfets, diodes irf.com irc sense resistors irctt.com kemet tantalum capacitors kemet.com magnetics inc toroid cores mag-inc.com microsemi diodes microsemi.com murata-erie inductors, capacitors murata.co.jp nichicon capacitors nichicon.com on semiconductor diodes onsemi.com panasonic capacitors panasonic.com pulse inductors pulseeng.com sanyo capacitors sanyo.co.jp sumida inductors sumida.com taiyo yuden capacitors t-yuden.com tdk capacitors, inductors component.tdk.com thermalloy heat sinks aavidthermalloy.com tokin capacitors nec - tokinamerica . com toko inductors tokoam.com united chemi-con capacitors chemi-com.com vishay/dale resistors vishay.com vishay/siliconix mosfets vishay.com w rth elektronik inductors we-online.com vishay/sprague capacitors vishay.com zetex small-signal discretes zetex.com recommended component manufacturers some of the recommended component manufacturers are listed in table 2. downloaded from: http:///
lt3758/lt3758a 27 3758afd typical applications 10v to 40v input, 48v output boost converter efficiency vs output current sense lt3758 v in v in 10v to 40v c in 4.7f50v x7r 2 v out 48v1a r s 0.012 r t 41.2k300khz gate fbx gnd intv cc shdn /uvlo sync rtss r3200k r4 32.4k c ss 0.68f c c2 100pf r c 10k c c1 10nf l118.7h 3758 ta02a r2464k d1 m1 r115.8k c vcc 4.7f10v x5r c out2 4.7f50v x7r 4 c out1 100f63v + c in , c out2 : murata grm32er71h475ka88l c out1 : panasonic ecg eev-tg1j101up d1: vishay siliconix 30bq060l1: pulse pb2020.223 m1: vishay siliconix si7460dp v c output current (a) 0.001 efficiency (%) 10 5040 30 20 60 70 80 90 100 0.01 0.1 3758 ta02b 1 v in = 40v v in = 24v v in = 10v start-up waveforms 5ms/div v out 20v/div i l1 2a/div 3758 ta02c v in = 24v downloaded from: http:///
lt3758/lt3758a 28 3758afd typical applications 12v output nonisolated flyback power supply efficiency vs output current start-up waveform sense lt3758 v in d sn v in 36v to 72v c in 2.2f100v x7r 63.4k200khz gate fbx gnd intv cc shdn /uvlo sync rtss 0.022f 100v t1 1,2,3 (series) 4,5,6(parallel) 1m44.2k 0.47f 100pf 10k 10nf 0.030 5.1 1n4148 15.8k1% 105k1% c vcc 4.7f10v x5r v out 12v1.2a 3758 ta03a c out 47fx5r 6.2k d1 sw m1 c in : murata grm32er72a225ka35l t1: coiltronics vp2-0066m1: vishay siliconix si4848dy d1: on semiconductor mbrs360t3gd sn : vishay siliconix es1d c out : murata grm32er61c476me15l v c output current (a) 0.01 efficiency (%) 20 5040 30 60 70 80 90 100 0.1 1 3758 ta03b 10 v in = 48v 5ms/div v out 5v/div 3758 ta03c v in = 48v frequency foldback waveforms when output short-circuit 20s/div v out 5v/div v sw 50v/div 3758 ta03d v in = 48v downloaded from: http:///
lt3758/lt3758a 29 3758afd 10ms/div v out1 , v out2 20v/div 3758 ta04b v in = 12v v out1 v out2 2s/div v sw 50v/div v out2 1v/div (ac) v out1 1v/div (ac) 3758 ta04c typical applications vfd (vacuum fluorescent display) flyback power supply start-up waveforms switching waveforms sense lt3758 v in v in 9v to 16v c in 22f25v 63.4k200khz gate fbx gnd intv cc shdn /uvlo sync rtss c out2 2.2f100v x7r t1 1, 2, 3 45 6 178k32.4k 0.47f 47pf 10k 10nf 0.019 0.5w 1.62k 95.3k d1 d2 c vcc 4.7f10v x5r v out 96v80ma v out2 64v40ma 3758 ta04a c out1 1f100v x7r sw m1 c in : murata grm32er61e226ke15l c out1 : murata grm31cr72a105k01l c out2 : murata grm32er72a225ka35l d1: vishay siliconix es1d d2: vishay siliconix es1cm1: vishay siliconix si4100dy t1: coiltronics vp1-0102 (*primary = 3 windings in parallel) 220pf 22 v c downloaded from: http:///
lt3758/lt3758a 30 3758afd typical applications 36v to 72v input, 3.3v output isolated telecom power supply sense lt3758 v in intv cc bav21w fdc2512 0.03 v in 36v to 72v c in 2.2f100v x7r 63.4k 200khz gate fbx gnd shdn /uvlo sync rtss 0.022f 100v 4.7f25v x5r 1m44.2k 0.47f v out + 3.3v3a v out - 3758 ta05a 5.6k 16k 4.7f 25v x5r 10 274 bas516 ps2801-1 bas516 2 43 8 7 6 ups840 5 1 0.47f lt4430 47nf 1f v in gnd opto comp oc 0.5v fb 47pf 2k 22.1k 100k bat54cwtig 2200pf 250vac 100pf c out 100f6.3v 3 pa1277nl v c output current (a) 0.01 efficiency (%) 20 5040 30 60 70 80 90 100 0.1 1 3758 ta05b 10 v in = 36v v in = 72v v in = 48v efficiency vs output current downloaded from: http:///
lt3758/lt3758a 31 3758afd typical applications 18v to 72v input, 24v output sepic converter sense lt3758a v in v in 18v to 72v c in2 2.2f100v x7r c dc 2.2f 100v x7r, 2 v out 24v1a 0.025 m1 41.2k300khz gate fbx gnd intv cc shdn /uvlo sync rtss ? ? 232k20k 0.47f 10nf 10k l1a l1b d1 c in1 : panasonic eee2aa100up c in2 , c dc : taiyo yuden hmk325b7225kn-t c out1 : murata grm31cr61e106ka12l c out2 : kemet t495x336k035as 3758 ta06a 280k1% 20k1% c out1 10f25v x5r 4 c vcc 4.7f10v x5r l1a, l1b: coiltronics drq127-470m1: fairchild semiconductor fdms2572 d1: on semiconductor mbrs3100t3g v c c in1 10f100v c out1 33f35v 2 + + efficiency vs output current output current (a) 0.001 10 efficiency (%) 3020 40 50 60 70 80 90 100 0.01 0.1 3758 ta06b 1 v in = 72v v in = 48v v in = 18v load step waveform 500s/div v out 2v/div ac-coupled i out 1a/div 0a 1a 3758 ta06c v in = 48v start-up waveform 2ms/div v out 10v/div il 1a + il 1b 1a/div 3758 ta06d v in = 48v 50s/div v sw 50v/div v out 20v/div il 1a + il 1b 2a/div 3758 ta06e v in = 48v frequency foldback waveforms when output short-circuit downloaded from: http:///
lt3758/lt3758a 32 3758afd typical applications 10v to 40v input, C12v output inverting converter sense lt3758a v in v in 10v to 40v c in2 4.7f50v x7r 2 c dc 2.2f 100v x7r, 2 0.015 m1 41.2k300khz gate fbx gnd intv cc shdn /uvlo sync rtss ? 0.47f 10k l1a 3758 ta07a c vcc 4.7f10v x5r v c c in1 4.7f50v 2 c out2 47f20v 2 + + r1200k r2 32.4k 6.8nf ? l1b d1 v out C12v2a 105k7.5k c out1 22f16v x5r 4 c in1 : kemet t495x475k050as c in2 , c dc : murata grm32er71h475ka88l c out1 : murata grm32er61c226ke20 c out2 : kemet t495x476k020as d1: vishay siliconix 30bq060l1a, l1b: coiltronics drq127-150 m1: vishay siliconix si7850dp efficiency vs output current output current (a) 0.001 10 efficiency (%) 3020 40 50 60 70 80 90 100 0.01 0.1 1 3758 ta07b 10 v in = 40v v in = 24v v in = 10v load step waveforms 500s/div v out 1v/div ac-coupled i out 1a/div 0a 1a 3758 ta07c v in = 24v start-up waveforms 5ms/div v out 5v/div il 1a + il 1b 2a/div 3758 ta07d v in = 24v 50s/div v sw 20v/div v out 10v/div il 1a + il 1b 5a/div 3758 ta07e v in = 24v frequency foldback waveforms when output short-circuit downloaded from: http:///
lt3758/lt3758a 33 3758afd package description 3.00 0.10 (4 sides) note:1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50bsc 0.70 0.05 3.55 0.05 packageoutline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notchr = 0.20 or 0.35 45 chamfer downloaded from: http:///
lt3758/lt3758a 34 3758afd package description msop (mse) 0911 rev h 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc 0.305 0.038 (.0120 .0015) typ bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 0.0508 (.004 .002) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29ref mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev h) downloaded from: http:///
lt3758/lt3758a 35 3758afd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 3/10 deleted bullet from features and last line of description updated all sections to include h-grade and military grade deleted vendor telephone information from table 2 in applications information section revised ta 04 and ta 04c in typical applications replaced related parts list 1 2 to 7 2629 36 b 5/10 revised last sentence of sync pin description updated block diagram revised value in last sentence of programming turn-on and turn-off thresholds in the shdn/uvlo pin section revised penultimate sentence of operating frequency and synchronization section 89 1013 c 5/11 revised mp-grade temperature range in absolute maximum ratings and order information revised note 2revised formula in applications information 24 19 d 07/12 added lt3758a version throughout updated block diagram 9 updated programming the output voltage section 13 updated loop compensation section 14 updated the schematic and load step waveforms in the typical applications section 31, 32 downloaded from: http:///
lt3758/lt3758a 36 3758afd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0712 rev d ? printed in usa typical applications related parts 8v to 72v input, 12v output sepic converter sense lt3758 v in v in 8v to 72v c in 2.2f100v x7r 2 c dc 2.2f 100v x7r, 2 v out 12v2a 0.012 m1si7456dp 41.2k300khz gate fbx gnd intv cc shdn /uvlo sync rtss ? ? 154k32.4k 0.47f 10nf 10k l1a l1b d1 mbrs3100t3g 3758 ta08a 105k1% 15.8k1% c out2 10f16v x5r 4 c out1 47f20v 2 c vcc 4.7f10v x5r l1a, l1b: coiltronics drq127-220 + v c efficiency vs output current v in = 8v output current (a) 10 efficiency (%) 3020 40 50 60 70 80 90 100 3758 ta08b 0.001 0.01 0.1 1 10 v in = 72v v in = 42v part number description comments lt3757a boost, flyback, sepic and inverting controller 2.9v v in 40v, current mode control, 100khz to 1mhz programmable operation frequency, 3mm 3mm dfn-10 and msop-10e packages lt3759 boost, sepic and inverting controller 1.6v v in 42v, current mode control, 100khz to 1mhz programmable operation frequency, msop-12e packages lt3957a boost, flyback, sepic and inverting controller with 5a, 40v switch 3v v in 40v, current mode control, 100khz to 1mhz programmable operation frequency, 5mm 6mm qfn package lt3958 boost, flyback, sepic and inverting controller with 3.3a, 84v switch 5v v in 80v, current mode control, 100khz to 1mhz programmable operation frequency, 5mm 6mm qfn package lt3573/lt3574/lt3575 40v isolated flyback converters monolithic no-opto flybacks with integrated 1.25a/0.65a/2.5a switch lt3511/lt3512 100v isolated flyback converters monolithic no-opto flybacks with integrated 240ma/420ma switch lt3798 offline isolated no opto-coupler flyback controller with active pfc v in and v out limited only by external components, msop-16 package lt3799/lt3799-1 offline isolated flyback led controllers with active pfc v in and v out limited only by external components, msop-16 package downloaded from: http:///

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